September 2017

Conference Paper

Design of a low parasitic inductance SiC power module with double-sided cooling

By:
Yang, Fei; Liang, Zhenxian; Wang, Zhiqiang ; Wang, Fei
Page Number:
3057-3062
Book Title:
2017 IEEE Applied Power Electronics Conference and Exposition (APEC)
Publication Date:
September 13, 2017
Conference Name:
IEEE Applied Power Electronics Conference and Exposition (APEC)
Conference Location:
Tampa, Florida, United States of America
Conference Sponsor:
IEEE Industry Applications Society, IEEE Power Electronics Society
View DOI Listing:
https://doi.org/10.1109/APEC.2017.7931132

Abstract

In this paper, a low-parasitic inductance SiC power module with double-sided cooling is designed and compared with a baseline double-sided cooled module. With the unique 3D layout utilizing vertical interconnection, the power loop inductance is effectively reduced without sacrificing the thermal performance. Both simulations and experiments are carried out to validate the design. Q3D simulation results show a power loop inductance of 1.63 nH, verified by the experiment, indicating more than 60% reduction of power loop inductance compared with the baseline module. With 0Ω external gate resistance turn-off at 600V, the voltage overshoot is less than 9% of the bus voltage at a load of 44.6A.